The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a data sampling circuit.
Synchronous DRAMs, which operates in synchronization with a system clock signal, have been developed for the high speed operation of semiconductor memory devices. Also, dual data rate (DDR) synchronous DRAMs and Rambus DRAMs, to which data is input and from which data is output in synchronization with the rising and falling edges of a clock signal, have recently been developed to satisfy demands for higher operation frequency.
FIG. 1 is a circuit diagram of a data sampling circuit using a conventional DDR method. FIG. 2 is a timing diagram of the data sampling circuit using the DDR method, shown in FIG. 1.
Referring to FIGS. 1 and 2, in the data sampling circuit of the conventional DDR method, a flip-flop 11 samples data Data1 input through an input and output pad D.sub.Q and outputs the sampled data to a data input and output line D.sub.IO at the falling edge of a clock signal CLOCK, i.e., where the level of the clock signal CLOCK is transited from a logic "high" level to a logic "low" level. Also, a flip-flop 13 samples data Data2 input through the input and output pad D.sub.Q and outputs the sampled data to the data input and output line D.sub.IO at the rising edge of the clock signal CLOCK, i.e., where the level of the clock signal CLOCK transits from the logic "low" level to the logic "high" level.
Therefore, according to the data sampling scheme of the conventional DDR method, it is possible to sample only two data items during one cycle (t.sub.CYCLE) of the clock signal (CLOCK).